1. Field of the Invention
The present invention relates generally to a system and method of providing error detection and correction capability in an integrated circuit (IC) using redundant logic cells and an embedded field programmable gate array (FPGA). The embedded FPGA provides for in circuit emulator (ICE) breakpoint and logic error correction (EC). The present invention provides flexible embedded logic engineering changes within the IC chip without requiring the contents of the latches of the logic function to be scanned to an external boundary, to make an EC change externally.
The EC method of the present invention can be used either during product design and development, or as a logic fix post-silicon fabrication. The subject invention also has application in evaluating error recovery of an IC chip design, wherein data errors can be injected through the embedded FPGA structures, and then the logic function IC design is evaluated as to how well it handles error recovery.
2. Discussion of the Prior Art
In the present state of the art, ICE structures have been designed and used primarily for debugging the development code of logic functions such as microprocessor IC logic functions. The ICE structures are used to monitor the operation of an instruction stream executing within a microprocessor IC. The primary function of the ICE structures is to debug development code by running an application code, setting a breakpoint in the execution of the application code, scanning the data in content registers, and mapping the data to a viewer screen. This allows a user to change the content of a memory image or register, and then continue to run the application code.
One limitation of current ICE structures is that they are not designed to fix logic structures or logic errors within the design of a microprocessor IC. The assumption of the ICE designed function is that the current microprocessor logic function works, and that the ICE structures are being used primarily for debugging the development code of the microprocessor logic function.
Present state of the art methods of designing an IC incorporate embedded logic EC structures in the IC that require the contents of the embedded logic EC structures to be scanned to an external boundary, and then any changes to the instruction stream are made externally.